Overview:

On a Basys 3 FPGA board, I implemented a multi-stage digital system in VHDL that combined counters, seven-segment display control, and a Mealy finite state machine (FSM). The project focused on designing, integrating, and debugging synchronous logic on real hardware—using switches, buttons, LEDs, and the 7-segment display as both inputs and visual feedback.

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Tools and Techniques Used:

• VHDL

• Basys 3 FPGA Board

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Process:

• Programmed modular VHDL components—including counters, clock dividers, seven-segment display drivers, and a Mealy FSM—then integrated them through a top-level architecture with precise signal mapping and pin constraint assignments for the Basys 3 board.

• Tested and debugged directly on hardware, using onboard switches, push-buttons, LEDs, and the seven-segment display to verify correct increment/decrement behavior, FSM-driven mode changes, wrap-around logic, and real-time state transitions.

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Result:

The final system ran entirely on the Basys 3 FPGA and demonstrated:​

• A sequence-driven FSM controller that changed the counter’s behavior based on user input patterns.

• Correct visual feedback on LEDs , VGA display, and the 7-segment display, confirming the internal state and count value.

This project strengthened my ability to design and debug synchronous digital systems end-to-end—from RTL (VHDL) and state machines to pin constraints, timing behavior, and interaction with real hardware.