Overview:

I implemented and simulated a series of ALU- and control-related digital design components using VHDL programming language and the ModelSim simulation environment. The work focused on understanding how arithmetic and logic operations, registers, counters, and finite state machines (FSMs) interact in a display and hardware-style pipeline, and how to verify their behavior through waveform-driven testing.

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Tools and Techniques Used:

• VHDL

• ModelSim

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Process:

• VHDL Design & Structure: I wrote VHDL modules for core building blocks including registers, shift registers, counters, ROM/RAM structures, and an ALU controlled by a finite state machine. I explored both Mealy and Moore-style FSMs to drive control signals for operations.

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• FSM & Control Logic: Designed a simple controller that generates enable, load, and up/down signals based on input conditions and internal state. This included defining state transitions for different criteria.

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• Simulation in ModelSim: Using ModelSim, I created and managed projects and VHDL source files. Compiled and debugged the design iteratively. I ran multiple simulation scenarios to verify ALU operations under different input and opcode combinations

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Result:

The final simulations demonstrated a working set of VHDL components tied together through state-machine-driven control logic. I was able to validate ALU behavior and control signals visually through waveforms. These projects strengthened my ability to reason about digital systems at the signal and state level, and to use simulation tools like ModelSim not just for debugging, but as a way to prototype and verify hardware-oriented designs before implementation.